Sequential Implementation

References

• Slides adapted from CMU

Y86-64 Instruction Set

Building Blocks

• Combinational Logic
  • Compute Boolean functions of inputs
  • Continuously respond to input changes
  • Operate on data and implement control
• Storage Elements
  • Store bits
  • Addressable memories
  • Non-addressable registers
  • Loaded only as clock rises

Sequential Hardware Structure

• State
  • Program counter register (PC)
  • Condition code register (CC)
  • Register file
  • Memories
• Instruction flow
  • Read instruction at address specified by PC
  • Process through stages
  • Update program counter

Sequential Stages

• Fetch: read instruction from memory
• Decode: read program registers
• Execute: compute value or address
• Memory: read or write data
• Write back: write program registers
• PC: update program counter

Sequential Hardware Structure

Instruction Decoding

• Instruction format (10 bytes max)
  • Instruction byte: icode:ifun
  • Optional register byte: rA:rB
  • Optional constant word: valC

Executing Arithmetic/Logical Operation

• Fetch: read 2 bytes
• Decode: read operand registers
• Execute: perform operation and set condition codes
• Memory: do nothing
• Write back: update register
• PC update: increment PC by 2

Stage Computation: Arithmetic/Logical Operations

Executing rmmovq

• Fetch: read 10 bytes
• Decode: read operand registers
• Execute: compute effective address
• Memory: write to memory
• Write back: do nothing
• PC update: increment PC by 10

Stage Computation: rmmovq

Executing popq

• Fetch: read 2 bytes
• Decode: read stack pointer
• Execute: increment stack pointer by 8
• Memory: read from old stack pointer
• Write back: update stack pointer and write result to register
• PC update: increment PC by 2

Stage Computation: popq

Executing Conditional Moves

• Fetch: read 2 bytes
• Decode: read operand registers
• Execute: if not condition, then set destination register to 0xF
• Memory: do nothing
• Write back: update register (or not)
• PC update: increment PC by 2

Stage Computation: Conditional Move

Executing Jumps

• Fetch: read 9 bytes and increment PC by 9
• Decode: do nothing
• Execute: determine whether to take branch based on jump condition codes
• Memory: do nothing
• Write back: do nothing
• PC update: set PC to destination if branch taken or to incremented PC if not branch

Stage Computation: Jumps

Executing call

• Fetch: read 9 bytes and increment PC by 9
• Decode: read stack pointer
• Execute: decrement stack pointer by 8
• Memory: write incremented PC to new value of stack pointer
• Write back: update stack pointer
• PC update: set PC to Dest

Stage Computation: call

Executing ret

• Fetch: read 1 byte
• Decode: read stack pointer
• Execute: increment stack pointer by 8
• Memory: read return address from old stack pointer
• Write back: update stack pointer
• PC update: set PC to return address

Stage Computation: ret

Computation Steps

Computed Values

• Fetch
  • icode: instruction code
  • ifun: instruction function
  • rA: instruction register A
  • rB: instruction register B
  • valC: instruction constant
  • valP: incremented PC

Computed Values

• Decode
  • srcA: register ID A
  • srcB: register ID B
  • dstE: destination register E
  • dstM: destination register M
  • valA: register value A
  • valB: register value B

Computed Values

• Execute
  • valE: ALU result
  • Cnd: branch/move flag
• Memory
  • valM: value from memory

Sequential Hardware

Sequential Hardware

• Diagram key
  • Blue boxes: pre-designed hardware blocks
  • Gray boxes: control logic
  • White ovals: labels for signals
  • Thick lines: 64-bit word values
  • Thin lines: 4-8 bit values
  • Dotted lines: 1-bit values

Fetch Logic

Fetch Logic

• Predefined Blocks
  • PC: Register containing PC
  • Instruction memory: read 10 bytes (PC to PC+9)
    • signal invalid addresses
  • Split: divide instruction byte into icode and ifun
  • Align: get fields for rA, rB, and valC
• Control Logic
  • Instruction valid: is the instruction valid?
  • icode, ifun: generate no-op if invalid address
  • Need regids: does the instruction have a register byte?
  • Need valC: does this instruction have a constant word?

Decode Logic

Decode Logic

• Register File
  • Read ports A, B
  • Write ports E, M
  • Addresses are register IDs or 15 (0xF) (no access)
• Control Logic
  • srcA, srcB: read port addresses
  • dstE, dstM: write port addresses
• Signals
  • Cnd: indicate whether or not to perform conditional move (computed in execute stage)

Execute Logic

Execute Logic

• Units
  • ALU: implements 4 required functions and generates condition code values
  • CC: register with 3 condition codes
  • cond: computes conditional jump/move flag
• Control Logic
  • Set CC: should condition code register be loaded?
  • ALU A: input A to ALU
  • ALU B: input B to ALU
  • ALU fun: what function should ALU compute?

Memory Logic

Memory Logic

• Memory
  • Reads or writes memory word
• Control Logic
  • stat: what is instruction status?
  • Mem. read: should word be read?
  • Mem. write: should word be written?
  • Mem. addr.: select address
  • Mem. data: select data

PC Update Logic

• New PC
  • Select next value of PC

Sequential Summary

• Implementation
  • Express every instruction as series of simple steps
  • Follow same general flow for each instruction type
  • Assemble registers, memories, pre-designed combinational blocks
  • Connect with control logic
• Limitations
  • Too slow to be practical
  • In one cycle must propagate through instruction memory, register file, ALU, and data memory
  • Would need to run the clock very slowly
  • Hardware units only active for fraction of clock cycle